DRAM cell structure capable of high integration and fabrication method thereof

ABSTRACT

A DRAM cell structure capable of high integration includes a trench-type capacitor formed in a lower region of a trench, the trench being made vertically and cylindrically in a silicon substrate, and a transistor being formed vertically and cylindrically over the trench-type capacitor, the transistor being connected to the capacitor. A method for fabricating a DRAM cell structure capable of high integration includes the steps of (a) forming a trench vertically and cylindrically in a silicon substrate, (b) forming a trench-type capacitor having a cylindrical plate electrode and a storage node electrode on a lower region of the trench, (c) forming a vertical cylindrical transistor cell structure connected to the trench-type capacitor on an upper region of the trench.

FIELD OF THE INVENTION

[0001] The present invention relates to a DRAM cell structure capable ofhigh integration and a fabrication method thereof; and, moreparticularly, to a vertical cylindrical DRAM cell structure capable ofhigh integration connected to a trench-type capacitor and a fabricationmethod thereof. 4

BACKGROUND OF THE INVENTION

[0002] A DRAM is a device formed by combination of many memory cellscomposed of a transistor and a capacitor. Recently, DRAMs are beingintegrated in higher density in response to demands for larger memorycapacity. Therefore, techniques for reducing a memory cell size tointegrate more memory cells in a confined space have been required.

[0003]FIG. 1 illustrates a conventional DRAM cell structure. As shown inFIG. 1, a conventional DRAM cell structure includes a transistor deviceformed horizontally on a silicon substrate, and a capacitor devicehaving a plate electrode and a storage node electrode formed on astacked layer over the transistor device.

[0004] However, the conventional horizontal DRAM cell structure shown inFIG. 1 has drawbacks. First, integration density is limited due toword-line size and length. Second, it is difficult to secure a largeenough size of the capacitor for sufficient capacitance.

SUMMARY OF THE INVENTION

[0005] It is, therefore, an object of the present invention to provide avertical cylindrical DRAM cell structure connected to a trench-typecapacitor capable of high integration and a fabrication method thereof.

[0006] In accordance with one aspect of the present invention, there isprovided a DRAM cell structure capable of high integration, including: atrench-type capacitor formed in a lower region of a trench, the trenchbeing made vertically and cylindrically in a silicon substrate; atransistor formed vertically and cylindrically over the trench-typecapacitor, the transistor being connected to the capacitor.

[0007] In accordance with another aspect of the present invention, thereis provided a method for fabricating a DRAM cell structure capable ofhigh integration, including the steps of (a) forming a trench verticallyand cylindrically in a silicon substrate; (b) forming a trench-typecapacitor having a cylindrical plate electrode and a storage nodeelectrode on a lower region of the trench; (c) forming a verticalcylindrical transistor cell structure connected to the trench-typecapacitor on an upper region of the trench.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other objects and features of the present inventionwill become apparent from the following description of preferredembodiments given in conjunction with the accompanying drawings, inwhich:

[0009]FIG. 1 illustrates a conventional DRAM cell structure;

[0010]FIG. 2 depicts a silicon substrate on which a vertical cylindricaltrench is formed in accordance with a preferred embodiment of thepresent invention;

[0011] FIGS. 3A-3M explain a method for fabricating a verticalcylindrical DRAM cell in accordance with a preferred embodiment of thepresent invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0012] Hereinafter, a preferred embodiment of the present invention willbe described in detail with reference to the accompanying drawings.

[0013]FIG. 2 illustrates a layout for fabricating a vertical cylindricalDRAM cell having a trench-type capacitor in accordance with a preferredembodiment of the present invention. First, a vertical cylindricaltrench is formed on a silicon substrate 208 by using a trench mask 200and an isolation mask 202 patterned in circular form. Next, employing adamascene method, a word-line contact is formed by using a word-linemask 206 and a bit-line mask 204. And next, a bit-line contact plug isformed by using a bit-line contact mask 210. Bit-line electrode materialis deposited on the bit-line contact plug, and then a bit-line is formedby using a bit-line formation mask 204.

[0014] FIGS. 3A-3M illustrate a method for fabricating a DRAM cellconnected to a trench-type capacitor and formed vertically andcylindrically on a silicon substrate to thereby increase an integrationdensity in accordance with a preferred embodiment of the presentinvention. Hereinafter, a transistor device is assumed to be n-type, butthe same principle can be applied for p-type case as well.

[0015] In order to form a trench for fabricating a vertical cylindricalDRAM cell in a silicon substrate as shown in FIG. 2, a buried n-well 302is formed on a silicon substrate 300, and then a p-well 304 is formed onthe buried n-well 302 as illustrated in FIG. 3A. Next, a first oxidefilm 306, a first nitride film 308 and a second oxide film 310 aresequentially deposited, and then a photoresist layer for a trench maskpatterning is deposited on the second oxide layer 310. Next, through aphotolithography process and an etching process, a trench mask 312 isformed by patterning the photoresist on a portion to be etched formaking a trench. Then, the second oxide film 310, the first nitride film308 and the first oxide film 306 are sequentially etched by using thepatterned trench mask 312.

[0016] As illustrated in FIG. 3B, the trench mask 312 is then removed,and a cylindrical trench 318 for fabricating a vertical cylindrical DRAMcell is formed by etching a silicon substrate at the portion for makinga trench, wherein the second oxide layer 310 is used as an etching mask.The trench etching is performed by using a high dry etching selectionratio of oxide and silicon to a depth of about several micrometers ormore. Next, an LPTEOS layer 314 doped with n-type impurity, e.g.,phosphorous, is deposited and coated with photoresist, and then etchedback down to the p-well region 304. Next, the photoresist is removed,the exposed LPTEOS is removed by dry etching, and then a third oxidelayer 316 is deposited.

[0017] As illustrated in FIG. 3C, a plate electrode 320 is then formedin the buried n-well region 302 by doping the LPTEOS layer 314 withphosphorous and diffusing the phosphorous into the silicon substratethrough an annealing process. Next, the p-doped LPTEOS layer 314 and thethird oxide layer 316 are removed by wet etching.

[0018] Referring to FIG. 3D, a storage capacitor insulation film 322 anda storage node 324 formed by doping polysilicon are sequentiallydeposited on a surface of the silicon substrate of FIG. 3C. A fourthoxide layer 326 is then stacked in the capacitor-formed trench tothereby fill the trench. Next, the fourth oxide layer 326 is etched backup to the plate electrode 320 by using a high selection ratio of oxideand poly.

[0019] As illustrated in FIG. 3E, a fifth oxide layer 328, having athickness of about several hundred angstroms, is then formed by thermaloxidation on a trench sidewall. Next, a storage node contact plug 330 issequentially stacked to thereby fill the trench, and the fifth oxidelayer 328 is etched back and then removed by wet etching.

[0020] Referring to FIG. 3F, a sixth oxide film 332 is thinly formed bythermal oxidation on the trench sidewall over the storage node contactplug 330. Next, a seventh oxide film 334 is thickly stacked on thestorage node contact plug 330, and then etched back to thereby form aninsulation layer having a thickness of about several hundred angstromsor more. Next, a mask nitride film 336 is stacked on an inner surface ofthe sixth oxide layer 332 and then etched back.

[0021] Referring to FIG. 3G, the seventh oxide film 334 is wet-etched.Next, the trench is filled with phosphorous-doped polysilsicon 335 onthe storage node contact plug, and then it is etched back to therebyform a poly connector 338.

[0022] As illustrated in FIG. 3H, the poly connector layer 338 is thenannealed so that phosphorous with which the poly connector material,i.e., the polysilicon, is doped diffuses into an adjacent trenchsidewall silicon substrate to thereby form a source 339. Next, the masknitride film 336 is removed by wet etching, and an eighth oxide film 340is thickly deposited on the poly connector 338 to thereby fill thetrench and then etched back. A gate insulation film 342 is thendeposited on a trench sidewall over the eighth oxide film 340. And next,the trench over the eighth oxide film 340 is filled with polysilicon tothereby form a gate electrode 344 and an implanting process is performedto thereby form a drain 346 on a surface of the silicon substratebetween consecutive gate electrodes. At this step, the gate electrode344 is formed to protrude on the surface of the silicon substrate

[0023] Referring to FIG. 3I, a caping nitride film is deposited on theentire silicon substrate, and then patterned to be removed by using aphotoresist isolation mask 350 patterned through a photolithographyprocess and an etching process, thereby exposing the drain 346.

[0024] As illustrated in FIG. 3J, the photoresist isolation mask 350 isremoved, and then the silicon substrate is dry-etched by a reactive ionetching (RIE) method employing the patterned caping nitride film 348 asa hard mask, to thereby expose the buried n-well region 302. The purposeof this etching process is isolating transistor devices in adjacenttrenches from each other. A device isolation hole, being made duringthis etching process, preferably extends down to the buried n-wellregion 302. However, it is allowable that it extends down to theself-aligned source 339. Next, a device-isolating planarization oxidefilm 352 is thickly stacked in the device isolation hole, and then thesilicon surface is planarized through a CMP process.

[0025] Referring to FIG. 3K, the device-isolating planarization oxidefilm 352 and the caping nitride film 348 are sequentially dry-etched byusing a photoresist word-line mask 354 patterned through aphotolithography process and an etching process, to thereby expose thegate electrode 344 so that a word-line contact hole 356 is formed.

[0026] As illustrated in FIG. 3L, the photoresist word-line mask 354 isthen removed, and the word-line contact hole 356 is filled withword-line electrode material, e.g., poly, poly electrode or tungsten, aword-line contact 359 is formed through a CMP process, and then aplanarization oxide film 358 is deposited on the word-line 359. Next,the planarization oxide film 358 and the device-isolating planarizationoxide film 352 are sequentially dry-etched by using a photoresistbit-line contact formation mask 360 patterned through a photolithographyprocess and an etching process, to thereby expose the drain region sothat a bit-line contact hole 362 is formed.

[0027] Referring to FIG. 3M, the bit-line contact hole 362 is filledwith bit-line electrode material, and then a contact plug 364 is formedby planarization through the CMP process. Next, bit-line electrodematerial 366 is deposited on the contact plug 364. Then, performing abit-line masking process, a bit-line is formed vertically to theword-line 359.

[0028] While the invention has been shown and described with respect tothe preferred embodiments, it will be understood by those skilled in theart that various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

[0029] In accordance with the present invention, a cylindrical trench isformed in a silicon substrate, and a capacitor and a transistor areformed vertically and cylindrically in the trench, to thereby reduce arestraint of word-line size and length so that a high integration can beachieved.

What is claimed is:
 1. A DRAM cell structure capable of highintegration, comprising: a trench-type capacitor formed in a lowerregion of a trench, the trench being made vertically and cylindricallyin a silicon substrate; a transistor formed vertically and cylindricallyover the trench-type capacitor, the transistor being connected to thecapacitor.
 2. The DRAM cell structure of claim 1, wherein thetrench-type capacitor including: a plate electrode formed by beingdiffused into the silicon substrate of a lower sidewall of the trench;an insulator formed by being thinly deposited on the lower sidewall ofthe trench, the insulator being adjacent to the plate electrode; astorage node electrode formed on the insulator, corresponding to theplate electrode.
 3. The DRAM cell structure of claim 2, wherein theplate electrode is formed by diffusing n-type impurity of an LPTEOSlayer into the silicon substrate through an annealing process, theLPTEOS layer being thinly deposited on the silicon substrate of thelower sidewall of the trench.
 4. The DRAM cell structure of claim 3,wherein an oxide film is deposited by coating on a surface of the LPTEOSlayer, the oxide film preventing the n-type impurity of the LPTEOS layerfrom being effused into the trench during the annealing process.
 5. TheDRAM cell structure of claim 4, wherein the LPTEOS and the oxide filmare removed by dry etching after the plate electrode being formedthrough the annealing process.
 6. The DRAM cell structure of claim 3,wherein the plate electrode is formed in a buried n-well region in thesilicon substrate.
 7. The DRAM cell structure of claim 2, wherein theinsulator is formed by making a capacitor insulation film on the lowersidewall of the trench, the capacitor insulation film being capable ofcharge accumulation.
 8. The DRAM cell structure of claim 2, wherein thestorage node electrode is formed by depositing a polysilicon layer on aninner surface of the insulator in the trench, corresponding to the plateelectrode.
 9. The DRAM cell structure of claim 8, wherein an oxide filmis stacked in the trench in which the storage electrode is formed. 10.The DRAM cell structure of claim 1, wherein the transistor includes: astorage node contact plug stacked over the storage electrode; a sourceformed by being diffused into an n- and p-well region of the siliconsubstrate of the trench sidewall; a poly connector stacked over thestorage node contact plug, the poly connector connecting the plug andthe source; a nitride film or an oxide film stacked over the polyconnector to thereby isolate a gate electrode and the poly connector; agate electrode stacked over the nitride film, the gate electrode beingconnected to a word-line; a gate isolation film deposited on the siliconsubstrate of the trench sidewall adjacent to the gate electrode; a drainformed through an implanting process between gate electrodes, the drainbeing connected to a bit-line.
 11. The DRAM cell structure of claim 10,wherein the storage node contact plug is formed through a process ofdepositing an oxide film on the trench sidewall over the storage nodeelectrode and stacking a contact conductor in the trench on which theoxide film is formed to thereby connect to the storage node electrode.12. The DRAM cell structure of claim 11, wherein the storage nodecontact plug is formed in the buried n-well region and an n-well regionof the silicon substrate in the trench.
 13. The DRAM cell structure ofclaim 11, wherein the oxide film is formed by thermal oxidation to adepth of about several hundred angstroms or more.
 14. The DRAM cellstructure of claim 13, wherein the oxide film is removed by wet etchingafter the storage node contact plug is formed.
 15. The DRAM cellstructure of claim 10, wherein the poly connector is formed by stackingpolysilicon doped with n-type impurity over the storage node contactplug in the trench to thereby be connected to the storage node contactplug.
 16. The DRAM cell structure of claim 10, wherein the source isformed by diffusing n-type impurity of poly connector material into anadjacent silicon substrate of the trench sidewall through an annealingprocess.
 17. The DRAM cell structure of claim 16, wherein the source isformed by being diffused into the n-well region of the silicon substratein the trench.
 18. The DRAM cell structure of claim 10, wherein the gateelectrode is formed by stacking polysilicon in the trench over thenitride film.
 19. The DRAM cell structure of claim 18, wherein the gateelectrode protrudes on the silicon substrate to a height of aboutseveral hundred angstroms or more.
 20. The DRAM cell structure of claim19, wherein the gate electrode is connected to a word-line of a DRAMcell via a word-line contact hole, the word-line contact hole beingformed over the gate electrode by etching.
 21. The DRAM cell structureof claim 20, wherein a word-line contact plug is formed by depositingpoly electrode or tungsten in the word-line contact hole to therebyconnect the gate electrode and the word-line.
 22. The DRAM cellstructure of claim 10, wherein the drain is connected to the bit-line ofthe DRAM cell via a bit-line contact hole, the bit-line contact holebeing formed over the drain by etching.
 23. The DRAM cell structure ofclaim 22, wherein a bit-line contact plug is formed by depositing poly,poly electrode or tungsten in the bit-line contact hole, to therebyconnect the bit-line and the drain.
 24. The DRAM cell structure of claim22, wherein a device isolation film is formed between the drain regionand the p-well region to thereby isolate transistor devices in adjacenttrenches.
 25. The DRAM cell structure of claim 24, wherein the deviceisolation film is of SOI structure for a device unit, the deviceisolation film being formed by stacking an oxide film on a deviceisolation hole, the device isolation hole being formed in the drainregion and the p-well region by etching.
 26. The DRAM cell structure ofclaim 24, wherein the bit-line connects two transistor devices inadjacent trenches.
 27. A method for fabricating a DRAM cell structurecapable of high integration, comprising the steps of: (a) forming atrench vertically and cylindrically in a silicon substrate; (b) forminga trench-type capacitor having a cylindrical plate electrode and astorage node electrode on a lower region of the trench; (c) forming avertical cylindrical transistor cell structure connected to thetrench-type capacitor on an upper region of the trench.
 28. The methodof claim 27, wherein the step (a) includes the steps of: (a1)sequentially depositing a first oxide film, a nitride film and a secondoxide film on an upper surface of the silicon substrate; (a2) depositinga photoresist layer over the second oxide film; (a3) forming a trenchmask by patterning the photoresist through a photolithography processand an etching process; (a4) sequentially etching the second oxide film,the nitride film and the first oxide film by using the patterned trenchmask; (a5) forming a cylindrical trench by etching the second oxidelayer at the silicon substrate of trench-forming portion by using anetching hard mask.
 29. The method of claim 28, wherein the trenchetching in the step (a5) is performed by using a high dry etchingselection ratio through a blanket dry etching method to a depth of somemicrometers or more.
 30. The method of claim 27, wherein the step (b)includes the steps of: (b1) forming a plate electrode on a siliconsubstrate of a lower sidewall of the trench; (b2) forming an insulatoron the lower sidewall of the trench in which the plate electrode isformed, the insulator being capable of charge accumulation; (b3) forminga storage node electrode on the lower sidewall of the trench on whichthe insulator is deposited, corresponding to the plate electrode. 31.The method of claim 30, wherein the step (b1) includes the steps of:(b11) depositing an LPTEOS layer doped with n-type impurity on thesilicon substrate of the lower sidewall of the trench; (b12) coating theLPTEOS layer with photoresist, etching back and then removing theexposed LPTEOS layer by wet etching; (b13) removing the photoresist filmand then depositing an oxide layer thereon; (b14) forming a plateelectrode by diffusing the n-type impurity of the LPTEOS layer into thesilicon substrate of the lower sidewall of the trench through anannealing process.
 32. The method of claim 31 further including the stepof: (b15) removing the LPTEOS layer and the oxide film formed on theLPTEOS layer by wet etching.
 33. The method of claim 31, wherein theplate electrode is formed in a buried n-well region in the siliconsubstrate.
 34. The method of claim 30, wherein at the step (b2) acapacitor insulation film is formed on the lower sidewall of the trenchin which the plate electrode is formed, the capacitor insulation filmbeing capable of charge accumulation.
 35. The method of claim 30,wherein at the step (b3) a polysilicon layer doped with n-type impurityis deposited on the insulator formed in the trench, corresponding to theplate electrode.
 36. The method of claim 30 further including the stepsof: (b4) filling the trench of the storage node electrode by stacking anoxide film; (b5) forming a trench-type capacitor by etching back thestacked oxide film to the electrode-forming position, wherein a high dryetching selection ratio of oxide and poly is used.
 37. The method ofclaim 27, wherein the step (c) includes the steps of: (c1) forming astorage node contact plug over the storage node electrode of thecapacitor in the lower trench; (c2) forming a poly connector over thestorage node contact plug, the poly connector connecting the plug andthe transistor source; (c3) forming a source on the silicon substrate ofthe trench sidewall adjacent to the poly connector, the source beingconnected to the poly connector; (c4) forming a gate electrode by beingstacked in the trench over the poly connector, the gate electrode beingconnected to the word-line; (c5) forming a drain between gate electrodesover the silicon substrate, the drain being connected to the bit-line.38. The method of claim 37, wherein the step (cl) includes the steps of:(c11) depositing an oxide film on the trench sidewall over the storagenode electrode; (c12) stacking a contact plug conductor over the storagenode electrode in the trench on which the oxide film is formed; (c13)forming a storage node contact plug by etching back the stacked contactplug.
 39. The method of claim 38, wherein the oxide film is formed bythermal oxidation to a depth of about several hundred angstroms or more.40. The method of claim 38 further including the step of: (c14) removingthe oxide film by wet etching.
 41. The method of claim 38, wherein thestorage node contact plug is formed in the buried n-well region and thep-well region in the silicon substrate of the trench.
 42. The method ofclaim 37, wherein the step (c2) includes the steps of: (c21) depositinga first oxide film on the trench sidewall over the storage node contactplug; (c22) stacking a second oxide film over the contact plug in thetrench on which the first oxide film is formed; (c23) etching back thesecond oxide film to thereby leave a thickness of the second oxide filmabout several hundred angstrom; (c24) depositing a mask nitride filmover the surface of the first oxide film formed on the trench sidewallover the second oxide film; (c25) removing the second oxide film by wetetching, wherein the mask nitride film is used as an etching mask; (c26)forming a poly connector by stacking n-doped poly silicon or PSG film inthe removed second oxide film portion and then etching back, the polyconnector being connected to the contact plug.
 43. The method of claim37, the source is formed by diffusing n-type impurity of the polyconnector material or p phosphorous in PSG film into the siliconsubstrate of an adjacent trench sidewall through an annealing process.44. The method of claim 43, wherein the poly connector material ispolysilicon doped with n-type impurity.
 45. The method of claim 43,wherein the source is formed by being diffused into the p-well region ofthe silicon substrate in the trench.
 46. The method of claim 37, whereinthe step (c4) includes the steps of: (c41) forming an insulation film bythickly stacking a nitride film or an oxide film over the poly connectorand then etching back, the insulation film isolating the gate and theconnector. (c42) depositing or thermally growing a gate oxide film onthe silicon substrate of the trench sidewall over the insulation film;(c43) forming a gate electrode by stacking polysilicon in the trench onwhich the gate oxide film is formed.
 47. The method of claim 46, whereinthe gate electrode protrudes on a surface of the silicon substrate to aheight of about several angstroms.
 48. The method of claim 37 furtherincluding: (c6) forming a device isolation film between transistordevices in adjacent trenches; (c7) connecting the gate electrode to theword-line; (c8) connecting the drain to the bit-line.
 49. The method ofclaim 48, wherein the step (c6) includes the steps of: (c61) depositinga caping nitride film on the gate electrode; (c62) depositing aphotoresist layer over the nitride film; (c63) forming a deviceisolation mask by patterning the photoresist through a photolithographyprocess and an etching process; (c64) patterning the nitride film byusing the isolation mask; (c65) etching down to the buried n-well regionof the silicon substrate by using the patterned nitride as a hard mask;(c66) stacking a device isolation oxide film on the etched deviceisolation hole and planarizing the silicon substrate through CMPprocess.
 50. The method of claim 49, wherein the device isolation holeis formed by RIE dry etching.
 51. The method of claim 48, wherein thestep (c7) includes the steps of: (c71) forming a photoresist layer overthe device isolation oxide film; (c72) forming a word-line mask bypatterning the photoresist through a photolithography process and anetching process; (c73) forming a word-line contact hole by sequentiallyetching the device isolation film and the caping nitride film, using theword-line mask; (c74) forming a word-line connected to the gateelectrode by stacking a word-line electrode material in the word-linecontact hole, and then planarizing through a CMP process.
 52. The methodof claim 48, wherein the step (c8) includes the steps of: (c81)depositing a planarization oxide film over the word-line; (c82) forminga photoresist layer over the planarization oxide film; (c83) forming abit-line contact formation mask by patterning the photoresist through aphotolithography process and an etching process; (c84) forming abit-line contact hole by sequentially etching the planarization oxidefilm and the device isolation planarization oxide film down to the drainregion, using the bit-line contact mask; (c85) forming a bit-linecontact plug by filling the bit-line contact hole with bit-lineelectrode material, and then planarizing through a CMP process; (c86)forming a bit-line vertical to the word-line over the bit-line contactplug by bit-line masking.
 53. The method of claim 52, wherein thebit-line connects drains of two transistor devices in adjacent trenches.